Semiconductor-On-Insulator Materials for Nanoelectronics Applications

Semiconductor-on-insulator materials for nanoelectronics applications
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Tavernier and. Piro00, A. Pirovano, G. Lacaita, R.

Semiconductor On Insulator Materials for Nanoelectronics Applications Engineering Materials

Zandler, and. Richard, F. Aniel, G. Fishman, N. Cavassilassah72, ]. Sah et al. Shim01 and. DigSmit54] C.

Smith " Piezoresistance effect in Germanium and Silicon , pp. Materials, C. Technologies, S. Low-power-mobile-multimediasury]-suryagandh, M. Arg et al.

Top Authors

IEEE International , pp. Wang and M. Webe06 and. Yang, M. Leong, L. Shi, K.

SemiconductorOnInsulator Materials for Nanoelectronics Applications by Nazarov & Alexei | Fruugo

Chan, V. Chant et al. Zilli, D.

Palestri, and L. Zhao, M. Takenaka, and S. Takagi , Comprehensive understanding of surface roughness and Coulomb scattering mobility in. Cros, P. Fenouillet-beranger, A. Perreau, F. Boeuf et al.

MATERIALS AND DEVICES

The benefit of this step graded approach, in terms of crystalline quality and surface morphology, has been demonstrated using X-Ray Diffraction, Atomic Force Microscopy and Transmission Electron Microscopy. Iordanidou et al. Solid State Sci. Tham, J. The spectrograms show recorded EEG data that correspond to an awake subject when the eyes are closed and open. The advent of graphene has ignited an enormous research interest on a number of 2D materials.

Ghibaudo, C. Ben-akkez, A. Cros, S. Margain, E. Borowiak, K. Gourvest, B. Bourdelle4, T. Nguyen et al. Ben-Akkez C. Diouf A. Cros C. Fenouillet-beranger, O. Perreau, I. Weber, and. The heat generated in the device regions propagates vertically to the semiconductor substrate via the BOX layer, SiO 2 , and laterally to the oxide isolation trenches in the non-device regions. The thermal conductivity of SiO 2 is about 1. A material with a lower thermal conductivity value means the material dissipates heat less effectively than the material with a higher value.

Therefore, the SiO 2 BOX layer inhibits cooling of the SOI devices and causes severe self-heating effects, which prevents the maximum available power consumption from increasing. Additionally, this increases the maximum interconnect temperature, and makes conduction cooling through the source, drain, and interconnects important. In addition, the device mobility is reduced as a result of the higher channel temperature, reducing the maximum drain saturation current and causing a negative differential conductance in the saturation region.

Thermal protection schemes designed for SOI circuits have been proposed using contact plugs in diodes. Although effective in dissipating heat, contact plugs consume large wafer area, introduce large delays, and increase manufacturing.

Therefore, there exists a strong need in the art for an SOI structure with a buried insulator layer that bleeds off extra carriers into a channel of the substrate, has a resistance and thermally conducts heat away from the device at a rate greater than conventional SiO 2 insulator layers at room temperature. According to one aspect of the invention, the invention is a semiconductor-on-insulator SOI structure having a polysilicon layer disposed between a semiconductor substrate and a semiconductor layer.

According to another aspect of the invention, the invention is a method of fabricating a semiconductor-on-insulator SOI structure having a polysilicon layer disposed between a semiconductor substrate and a semiconductor layer. The method includes the steps of depositing a polysilicon layer on a first semiconductor substrate and depositing a polysilicon layer on a second semiconductor substrate.

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Further, the method includes the step of creating a zone of weakness under a surface of one of the semiconductor substrates. Next, the method requires the placing of one of the semiconductor substrates on top of the other semiconductor substrate such that the polysilicon layer of the first semiconductor substrate is in contact with the polysilicon layer of the second semiconductor substrate.

Product information

The method also includes the step of breaking the zone of weakness of the one semiconductor substrate and repairing a damaged surface resulting from the breaking of the zone of weakness of the one semiconductor substrate. According to another aspect of the invention, the invention is a method of fabricating an SOI structure as described above. However, the method step of repairing the surface resulting from the breaking of the zone of weakness further includes the step of polishing the surface in order to remove residual weak zone damage.

According to another aspect of the invention, the invention is a method of fabricating an SOI structure as described in the first method above. The method further includes the additional step of fusing the polysilicon layer of the first semiconductor substrate with the polysilicon layer of the second semiconductor substrate. These and further features of the present invention will be apparent with reference to the following description and drawings, wherein:. In the detailed description that follows, identical components have been given the same reference numerals.

To illustrate the present invention in a clear and concise manner, the drawings may not necessarily be to scale and certain features may be shown in a partial schematic format. The present invention is a semiconductor on insulator SOI structure, and method of making the same, comprising an insulator layer of electrically resistive silicon, e. Electronic devices such as metal-oxide semiconductor field effect transistors, i. MOSFETs, may be formed in device regions of the semiconductor layer defined laterally by isolation regions such as shallow trench isolation STI regions and vertically by the insulator layer.

MOSFETs formed on such SOI structures will be significantly less affected by the FBE and self-heating due to the resistive silicon layer being made of a material with properties that allow leakage at a level approximately equal to the currently used material of SiO 2 while more efficiently dissipating heat due to a significantly higher thermal conductivity. The resistive silicon layer of doped or undoped polysilicon or the like has an electrical resistivity or specific resistance greater than that of the semiconductor substrate and the semiconductor layer. Specific resistance refers to the opposition presented by a material to the flow of electricity.

J. P. Colinge

Resistivity is an intrinsic property of a material independent of the amount or shape. Pure Si normally used in the substrate and semiconductor layer has a higher resistivity than metals, because the number of charge carriers is much reduced. Polysilicon would have a resistivity slightly higher than pure Si due to the arrangement of the lattice structure and the grain size.

Further, the leakage current through the resistive silicon layer can be tailored so that the total chip power consumption does not significantly increase. This is about 50 to about 85 times greater than the thermal conductivity of SiO 2. Since the resistive silicon layer has a substantially greater thermal conductivity than that of SiO 2 , improved heat dissipation can be obtained.

Semiconductor-On-Insulator Materials for Nanoelectronics Applications

That is if the resistive silicon layer has a suitable electrical resistivity for the operating frequency range of the semiconductor device. Also, the resistive silicon layer can be regarded as a dielectric concerning the parasitic capacitance between the substrate and a conductor formed over the device region.

It should be appreciated that the resistance and capacitance of the insulator layer is such that its RC time constant should be large enough that the semiconductor layer is generally electrically isolated from the semiconductor substrate with respect to alternating-current AC operation, while it is generally electrically connected to the semiconductor substrate with respect to very low frequency or direct-current DC operation. In other words, during low frequency operation the resistive silicon acts as a low frequency filter and allows the low frequency charge buildup, i.

On the other hand, during high frequency operation associated with the respective active devices the resistive silicon acts as a barrier to the high frequency currents passing through the insulating layer and isolates the active regions from the underlying substrate. An RC time constant greater than 1 usec is preferred. Therefore, the parasitic capacitance can be kept low. For example, when the operating frequency, or the applicable electric signal frequency of the semiconductor device is 1 GHz, the electrical resistivity of the resistive silicon layer is preferably 10 ohm-cm or greater.

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Now referring to FIG. The SOI structure 10 is formed using a semiconductor substrate 12 , a buried resistive silicon layer 14 formed on the semiconductor substrate 12 and a semiconductor layer 13 disposed on the resistive silicon layer The resistive silicon layer 14 in one embodiment is undoped polysilicon. However, the resistive silicon layer 14 may be of doped silicon that has the characteristics described herein for resistivity and thermal conductivity.

The electrical properties of polysilicon depend strongly on the grain structure of the film. The grain boundaries provide a potential barrier to the moving charge carriers and affect the conductivity of the films. Grain boundary and ionized impurity scattering are important factors limiting the mobility. The thermal conductivity of polysilicon is a strong function of the grain structure of the film. For fine grain films, the thermal conductivity is about 0.